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Atmel /ATSAM3A8C /UOTGHS /HSTPIPISR[0]

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Interpret as HSTPIPISR[0]

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXINI)RXINI 0 (TXOUTI)TXOUTI 0 (TXSTPI)TXSTPI 0 (PERRI)PERRI 0 (NAKEDI)NAKEDI 0 (OVERFI)OVERFI 0 (RXSTALLDI)RXSTALLDI 0 (SHORTPACKETI)SHORTPACKETI 0 (DATA0)DTSEQ 0 (0_BUSY)NBUSYBK 0 (BANK0)CURRBK 0 (RWALL)RWALL 0 (CFGOK)CFGOK 0PBYCT

NBUSYBK=0_BUSY, DTSEQ=DATA0, CURRBK=BANK0

Description

Host Pipe Status Register (n = 0)

Fields

RXINI

Received IN Data Interrupt
TXOUTI

Transmitted OUT Data Interrupt
TXSTPI

Transmitted SETUP Interrupt
PERRI

Pipe Error Interrupt
NAKEDI

NAKed Interrupt
OVERFI

Overflow Interrupt
RXSTALLDI

Received STALLed Interrupt
SHORTPACKETI

Short Packet Interrupt
DTSEQ

Data Toggle Sequence

0 (DATA0): Data0 toggle sequence

1 (DATA1): Data1 toggle sequence
NBUSYBK

Number of Busy Banks

0 (0_BUSY): 0 busy bank (all banks free)

1 (1_BUSY): 1 busy bank

2 (2_BUSY): 2 busy banks

3 (3_BUSY): 3 busy banks
CURRBK

Current Bank

0 (BANK0): Current bank is bank0

1 (BANK1): Current bank is bank1

2 (BANK2): Current bank is bank2
RWALL

Read-write Allowed
CFGOK

Configuration OK Status
PBYCT

Pipe Byte Count

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data